Many electronic devices use clock signals to coordinate operation of components. For example, electronic systems using synchronous dynamic random access memories (SDRAMs) commonly coordinate the SDRAM output with the system clock. Consequently, most SDRAMs and other components receive the system clock for synchronizing the SDRAMs' operations with the other components in the system.
Clock skew, however, disrupts the coordination between the system clock and the output signal of the SDRAM. Clock skew is a delay between the externally-supplied system clock signal and the signal used by the SDRAM output circuitry to generate the output signals. Several causes, including delays associated with the clock input buffer, drivers, and other resistive-capacitive circuit elements, contribute to clock skew.
Several solutions can correct clock skew to coordinate the system clock with the SDRAM clock. For example, some systems use delay-locked loops (DLLs) or phase-locked loops (PLLs) to lock the SDRAM output data to the system clock signal. DLLs and PLLs, however, require a relatively long time to lock onto the input signal. Further, temperature and voltage variations may degrade the performance of DLLs and PLLs.
Synchronized delay circuits are another popular deskewing solution, such as clock-synchronized delay (CSD) circuits and synchronized mirror delay (SMED) circuits. Synchronized delay circuits typically offer faster lock performance than DLLs and PLLs. For example, conventional SMD circuits may lock onto the input signal in two cycles; conventional CSD circuits may lock onto the input signal in a single cycle.
Referring to FIG. 1, a conventional CSD circuit 100 comprises an input buffer 102 to receive the system clock signal and provide it to a delay monitor circuit 104, a latch 106, and a variable delay line 108. The delay monitor circuit 104 inserts a desired delay into the signal and provides the delayed input signal to a measure delay line 110. The measure delay line 110 measures the difference between the delayed signal from the delay monitor circuit 104 and the system clock. The measured delay is communicated to the latch 106. The latch 106 is read by the variable delay line 108, and the variable delay line 108 generates a signal delayed by the same delay as measured by the measure delay line 110. The signal from the variable delay line 108 is then provided to a clock driver circuit 112 to amplify and distribute the synchronized signal.
The measure delay line 110 suitably measures the delay by receiving the input signal through a series of stages, each of which generates a single-bit signal to indicate whether the particular stage corresponds to the measured delay. For example, referring to FIG. 2, the measure delay line 110 may comprise a series of stages 210, each stage comprising a NAND gate 212 and an inverter 214. Each stage 210 provides a signal to the latch 106 to indicate whether the delay has been successfully measured by the stage 210. Thus, referring to FIG. 3, the latch 106 receives a digital word. The delay is successfully measured by the stage 210 that provides the first logic HIGH signal, which is referred to as the entry point 310, to the latch 106.
In some applications, such as portable battery-driven devices, synchronized delay circuits may consume excessive power and/or generate noise. The additional power consumption and noise generation is due to portions of the digital delay elements toggling unnecessarily. Further, a single synchronized delay circuit may be used to synchronize at many different frequencies. For especially slow frequencies, the sampling frequency of the synchronized delay circuit may be so high that all of the samples are taken before the first pulse of the input signal arrives, causing an overflow condition. In other words, the synchronized delay circuit cannot measure a delay exceeding a particular limit.